Modern integrated circuit testing methods typically rely on a testing methodology utilizing scan chains. Scan chains allow an increased ability to observe and control the device under test (DUT). Typically, testing methods utilizing scan chains operate in two modes. The first scan chain operation mode is the normal mode, in which the memory elements, or latches, of the integrated circuit perform their normal function. Generally, each latch occupies a position feeding an input into a logic operation. During the normal mode, the latch stores a logic value that is a product of the preceding logic operation, which feeds into the subsequent logic operation.
The second scan chain operation mode is the test mode. During the test mode, the latches of the integrated circuit connect into one or more long shift registers (the “scan chains”). The testing operation shifts test patterns into the scan chains. Generally, test patterns are a series of logic values arranged in the order of the scan chain latch they are to occupy. The circuit performs the logic operations based on the stored values shifted into the latches, typically for a single clock cycle. The latches subsequent to the logic operators store the logic value produced by the logic operations based on the values inputted through the scan chain.
The testing process shifts test responses out of the scan chains, as a test response pattern. The testing process compares the test response pattern to the fault-free test response pattern to determine whether the circuit under test is functioning correctly. The pattern of logic values produced by a normal operation of the circuit under test constitutes the fault-free test response pattern.
Scan design methodology facilitates simple automatic test pattern generation (ATPG) methods. Modern ATPG tools are able to generate deterministic tests. Generally, a deterministic test is a test that achieves almost complete fault coverage for a variety of types of fault models. However, for large circuits, using an approach based on ATPG alone is infeasible. Test approaches using only ATPG typically require a large test set size and a relatively long test time in order to achieve acceptable fault coverage. This large test set size requires excessive storage requirements. Built-in-self-testing (BIST) overcomes, to some extent, the excessive storage requirements for patterns created using ATPG.
BIST uses on-chip pseudo-random pattern generators to supply patterns to the scan chains. During testing, an operator serially feeds test responses into on-chip multiple input shift registers (MISR). The MISRs generate and store the resulting signatures from the test responses. Using the conventional test methodology, a system employing BIST compares the resulting test signatures to previously generated fault-free signatures for the DUT.
Although BIST can cover a significant portion of “stuck-at” faults (a fault model that sticks the output of a logic gate at a either a high logic value or a low logic value independent of the inputs to the logic gate), a typical testing operation also performs additional deterministic tests in order to target random-pattern-resistant (RPR) faults. Thus, an effective test methodology for large designs requires a hybrid testing scheme. This testing scheme includes ATPG for RPR faults not detected by BIST, and BIST to find a total set of deterministic test patterns that bring the fault coverage to the desired level.
While a hybrid-testing scheme does not consume the same amount of storage as a testing scheme relying on ATPG alone, the hybrid-testing scheme still consumes an excessive level of storage. To remedy this, compression methods sometimes accompany ATPG. Generally, compression methods reduce the size of a pattern set without lowering the fault detection rate of the patterns. Compression methods accomplish this result by reducing the amount of data that needs to be stored in the tester memory. Compression also reduces the test time for a given test data bandwidth.
But current compression schemes, especially pattern-merging schemes, suffer from significant drawbacks. As the density of modern circuits continues to grow, modern pattern-merging methods are unable to reduce to a manageable level the set of test patterns necessary to achieve the desired fault coverage. Consequently, modern pattern-merging methods require an increasing amount of storage space as circuit density increases.
The increased size of the set of test patterns necessary to achieve the desired fault coverage also dramatically increases the time needed to perform a test of a dense modern circuit. The testing unit must apply each individual test pattern to the circuit and each application of a test pattern requires a discrete amount of time. Therefore, as the total number of merged test patterns necessary to achieve the desired fault coverage for a dense circuit increases, the test requires an increasing amount of time to perform. The increased time required by the test operation negates one of the original advantages of compression and test pattern merging.
Therefore, there is a need for a method or system for improved test pattern compression that addresses at least some of the problems and disadvantages associated with conventional methods and systems.